Helprack is working with a customer to implement vectorization in their GCC based compiler. This customer develops licensable processor IPs for media processing. Learn how Helprack is developing a vectorizing compiler for their variable length vector processing units.

The customer has multiple processor cores with vector units of different sizes. These cores can operate on an entire vector register or any arbitrary parts of it based on a register mask. Besides, they have hundreds of instructions that do not have a direct equivalence in the C/C++ programming paradigm, which need to be implemented as intrinsics. These intrinsics also have a vector form. The customer wanted regular arithmetic and logical operations and these intrinsics to be vectorized for their cores. In addition, they wanted the tail of the loop to be converted into a linear code using the masking feature of the vector registers. The other features that their vector processor supported are striding and scatter/gather.

Helprack augmented the vectorizer in the GCC to implement the tail loop conversion to linear code, and also implemented an innovative mechanism to implement the intrinsics and their vectorized forms, such that the same scalar intrinsic can be called for any processor and the compiler generates vectorized code with the vector size suitable for that processor. Helprack also implemented the scatter/gather and striding operations in GCC for this family of processors.